A timing-driven soft-macro resynthesis method in interaction with chip floorplanning

In this paper, we present a complete chip design method which incorporates a soft-macro resynthesis method in interaction with chip floorplanning for area and timing improvements. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. Durin...

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Bibliographic Details
Main Authors: Hsiao-Pin Su, Wu, A.C.-H., Youn-Long Lin
Format: Conference Proceeding
Language:English
Subjects:
Chip scale packaging
Computer aided manufacturing
Computer science
Delay
Design methodology
Hardware design languages
Permission
Pulp manufacturing
Routing
Timing
Online Access:Request full text
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Summary:In this paper, we present a complete chip design method which incorporates a soft-macro resynthesis method in interaction with chip floorplanning for area and timing improvements. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs have demonstrated that by effectively relaxing the timing constraint of the non-critical modules and tightening the timing constraint of the critical modules, a design can achieve 13% to 30% timing improvements with little to no increase in chip area.
DOI:10.1109/DAC.1999.781323