Hierarchical test generation for analog circuits using incremental test development

In this paper, we propose an efficient test generation scheme for analog circuits consisting of embedded modules. The proposed scheme simplifies the test generation effort by incrementally generating tests for the individual embedded modules rather than for the full circuit. At each step of the test...

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Bibliographic Details
Main Authors: Voorakaranam, R., Chatterjee, A.
Format: Conference Proceeding
Language:English
Subjects:
Analog circuits
Circuit faults
Circuit simulation
Circuit testing
Contracts
Engines
Feedback circuits
Observability
Signal generators
System testing
Online Access:Request full text
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Description
Summary:In this paper, we propose an efficient test generation scheme for analog circuits consisting of embedded modules. The proposed scheme simplifies the test generation effort by incrementally generating tests for the individual embedded modules rather than for the full circuit. At each step of the test generation process, the test waveform is incrementally optimized. As input nodes to an embedded module are not directly accessible, the test optimization considers only those waveforms that can be justified from an embedded module input to a primary input of the circuit-under-test using a signal backtrace procedure. The "best" selected test is then evaluated at the full circuit level for controllability of the test stimulus and observability of the test results. In this manner, repeated evaluation of the full circuit over the search space of all test stimuli is not necessary and the complexity of test search can be reduced.
ISSN:1093-0167
2375-1053
DOI:10.1109/VTEST.1999.766679