High-Speed and Low-Latency ECC Processor Implementation Over GF( 2^) on FPGA

In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorit...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2017-01, Vol.25 (1), p.165-176
Main Authors: Khan, Zia U. A., Benaissa, Mohammed
Format: Article
Language:English
Subjects:
Algorithms
Clocks
Complexity theory
Cryptography
Curves
Delays
Elliptic curve cryptography
Field programmable gate arrays
Field-programmable gate array (FPGA)
Hardware
High speed
high-speed elliptic curve cryptography (ECC)
low latency
Microprocessors
Multiplication
Pipeline processing
pipelined bit-parallel multiplier
point multiplication (PM)
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c339t-26d1a26f938f75df50fb815828ed9c0fdd387952e9248871df93872654beaf733
cites cdi_FETCH-LOGICAL-c339t-26d1a26f938f75df50fb815828ed9c0fdd387952e9248871df93872654beaf733
container_end_page 176
container_issue 1
container_start_page 165
container_title IEEE transactions on very large scale integration (VLSI) systems
container_volume 25
creator Khan, Zia U. A.
Benaissa, Mohammed
description In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7).
doi_str_mv 10.1109/TVLSI.2016.2574620
format article
fullrecord <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_ieee_primary_7491370</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7491370</ieee_id><sourcerecordid>1855458082</sourcerecordid><originalsourceid>FETCH-LOGICAL-c339t-26d1a26f938f75df50fb815828ed9c0fdd387952e9248871df93872654beaf733</originalsourceid><addsrcrecordid>eNo9kE1Lw0AQhhdRsFb_gF4WvOghdT-y2d1jCf2CQAutHl3S7KymtEncTZX-e1NbnMvMwPPOwIPQPSUDSol-Wb1ly9mAEZoMmJBxwsgF6lEhZKS7uuxmkvBIMUqu0U0IG0JoHGvSQ9m0_PiMlg2AxXllcVb_RFneQlUc8ChN8cLXBYRQezzbNVvYQdXmbVlXeP4NHk_GT5i9P-NuHy8mw1t05fJtgLtz76PX8WiVTqNsPpmlwywqONdtxBJLc5Y4zZWTwjpB3FpRoZgCqwvirOVKasFAs1gpSe2RlCwR8RpyJznvo8fT3cbXX3sIrdnUe191Lw1VQsRCEcU6ip2owtcheHCm8eUu9wdDiTlaM3_WzNGaOVvrQg-nUAkA_wEZa8ol4b8_BGWS</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1855458082</pqid></control><display><type>article</type><title>High-Speed and Low-Latency ECC Processor Implementation Over GF( 2^) on FPGA</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Khan, Zia U. A. ; Benaissa, Mohammed</creator><creatorcontrib>Khan, Zia U. A. ; Benaissa, Mohammed</creatorcontrib><description>In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7).</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2016.2574620</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; Clocks ; Complexity theory ; Cryptography ; Curves ; Delays ; Elliptic curve cryptography ; Field programmable gate arrays ; Field-programmable gate array (FPGA) ; Hardware ; High speed ; high-speed elliptic curve cryptography (ECC) ; low latency ; Microprocessors ; Multiplication ; Pipeline processing ; pipelined bit-parallel multiplier ; point multiplication (PM)</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2017-01, Vol.25 (1), p.165-176</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c339t-26d1a26f938f75df50fb815828ed9c0fdd387952e9248871df93872654beaf733</citedby><cites>FETCH-LOGICAL-c339t-26d1a26f938f75df50fb815828ed9c0fdd387952e9248871df93872654beaf733</cites><orcidid>0000-0001-7524-9116</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7491370$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,786,790,27957,27958,55147</link.rule.ids></links><search><creatorcontrib>Khan, Zia U. A.</creatorcontrib><creatorcontrib>Benaissa, Mohammed</creatorcontrib><title>High-Speed and Low-Latency ECC Processor Implementation Over GF( 2^) on FPGA</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7).</description><subject>Algorithms</subject><subject>Clocks</subject><subject>Complexity theory</subject><subject>Cryptography</subject><subject>Curves</subject><subject>Delays</subject><subject>Elliptic curve cryptography</subject><subject>Field programmable gate arrays</subject><subject>Field-programmable gate array (FPGA)</subject><subject>Hardware</subject><subject>High speed</subject><subject>high-speed elliptic curve cryptography (ECC)</subject><subject>low latency</subject><subject>Microprocessors</subject><subject>Multiplication</subject><subject>Pipeline processing</subject><subject>pipelined bit-parallel multiplier</subject><subject>point multiplication (PM)</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><recordid>eNo9kE1Lw0AQhhdRsFb_gF4WvOghdT-y2d1jCf2CQAutHl3S7KymtEncTZX-e1NbnMvMwPPOwIPQPSUDSol-Wb1ly9mAEZoMmJBxwsgF6lEhZKS7uuxmkvBIMUqu0U0IG0JoHGvSQ9m0_PiMlg2AxXllcVb_RFneQlUc8ChN8cLXBYRQezzbNVvYQdXmbVlXeP4NHk_GT5i9P-NuHy8mw1t05fJtgLtz76PX8WiVTqNsPpmlwywqONdtxBJLc5Y4zZWTwjpB3FpRoZgCqwvirOVKasFAs1gpSe2RlCwR8RpyJznvo8fT3cbXX3sIrdnUe191Lw1VQsRCEcU6ip2owtcheHCm8eUu9wdDiTlaM3_WzNGaOVvrQg-nUAkA_wEZa8ol4b8_BGWS</recordid><startdate>201701</startdate><enddate>201701</enddate><creator>Khan, Zia U. A.</creator><creator>Benaissa, Mohammed</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0001-7524-9116</orcidid></search><sort><creationdate>201701</creationdate><title>High-Speed and Low-Latency ECC Processor Implementation Over GF( 2^) on FPGA</title><author>Khan, Zia U. A. ; Benaissa, Mohammed</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c339t-26d1a26f938f75df50fb815828ed9c0fdd387952e9248871df93872654beaf733</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Algorithms</topic><topic>Clocks</topic><topic>Complexity theory</topic><topic>Cryptography</topic><topic>Curves</topic><topic>Delays</topic><topic>Elliptic curve cryptography</topic><topic>Field programmable gate arrays</topic><topic>Field-programmable gate array (FPGA)</topic><topic>Hardware</topic><topic>High speed</topic><topic>high-speed elliptic curve cryptography (ECC)</topic><topic>low latency</topic><topic>Microprocessors</topic><topic>Multiplication</topic><topic>Pipeline processing</topic><topic>pipelined bit-parallel multiplier</topic><topic>point multiplication (PM)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Khan, Zia U. A.</creatorcontrib><creatorcontrib>Benaissa, Mohammed</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library Online</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Khan, Zia U. A.</au><au>Benaissa, Mohammed</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>High-Speed and Low-Latency ECC Processor Implementation Over GF( 2^) on FPGA</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2017-01</date><risdate>2017</risdate><volume>25</volume><issue>1</issue><spage>165</spage><epage>176</epage><pages>165-176</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7).</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2016.2574620</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0001-7524-9116</orcidid><oa>free_for_read</oa></addata></record>
fulltext fulltext
identifier ISSN: 1063-8210
ispartof IEEE transactions on very large scale integration (VLSI) systems, 2017-01, Vol.25 (1), p.165-176
issn 1063-8210
1557-9999
language eng
recordid cdi_ieee_primary_7491370
source IEEE Electronic Library (IEL) Journals
subjects Algorithms
Clocks
Complexity theory
Cryptography
Curves
Delays
Elliptic curve cryptography
Field programmable gate arrays
Field-programmable gate array (FPGA)
Hardware
High speed
high-speed elliptic curve cryptography (ECC)
low latency
Microprocessors
Multiplication
Pipeline processing
pipelined bit-parallel multiplier
point multiplication (PM)
title High-Speed and Low-Latency ECC Processor Implementation Over GF( 2^) on FPGA
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-09-22T20%3A27%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=High-Speed%20and%20Low-Latency%20ECC%20Processor%20Implementation%20Over%20GF(%202%5E)%20on%20FPGA&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Khan,%20Zia%20U.%20A.&rft.date=2017-01&rft.volume=25&rft.issue=1&rft.spage=165&rft.epage=176&rft.pages=165-176&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2016.2574620&rft_dat=%3Cproquest_ieee_%3E1855458082%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c339t-26d1a26f938f75df50fb815828ed9c0fdd387952e9248871df93872654beaf733%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=1855458082&rft_id=info:pmid/&rft_ieee_id=7491370&rfr_iscdi=true