High-Speed and Low-Latency ECC Processor Implementation Over GF( 2^) on FPGA

In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorit...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2017-01, Vol.25 (1), p.165-176
Main Authors: Khan, Zia U. A., Benaissa, Mohammed
Format: Article
Language:English
Subjects:
Algorithms
Clocks
Complexity theory
Cryptography
Curves
Delays
Elliptic curve cryptography
Field programmable gate arrays
Field-programmable gate array (FPGA)
Hardware
High speed
high-speed elliptic curve cryptography (ECC)
low latency
Microprocessors
Multiplication
Pipeline processing
pipelined bit-parallel multiplier
point multiplication (PM)
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Summary:In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7).
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2016.2574620