A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

This paper presents a 4 \times time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b/cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls are simpl...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2016-02, Vol.51 (2), p.365-377
Main Authors: Chan, Chi-Hang, Zhu, Yan, Sin, Sai-Weng, Ben U, Seng-Pan, Martins, Rui Paulo
Format: Article
Language:English
Subjects:
Analog-to-digital conversion
Arrays
Calibration
Hardware
interleaving
Interpolation
Latches
multibit/cycle SAR
offset calibration
Switches
Timing
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Summary:This paper presents a 4 \times time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b/cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls are simplified with a proposed fractional DAC array switching scheme, thus reducing the design complexity and the hardware burden. A boundary detection code overriding (BDCO) is introduced to reduce error probability at the large error magnitude, by utilizing the extended time when the comparator is at reset and the DAC at settling. The floorplan of the front-end is optimized for important interleaving clock distributions, and a master-clock-control bootstrapped-switch technique is adopted to suppress the timing-skew effect among the channels. The unit capacitor has been designed to suit for the DAC structure which allows top-plate sharing in both directions, plus, the offset is calibrated on-chip with a clocking variable biasing transistor pair at the latch. Measurement results show that the prototype can achieve 5 GS/s with a total power consumption of 5.5 mW at 1 V supply in 65 nm CMOS technology. Besides, it exhibits a 30.76 dB SNDR and 43.12 dB SFDR at Nyquist, which yields a Walden FoM of 39 fJ/conversion-step.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2015.2493167