A space vector modulation method for common-mode voltage reduction in nested neutral point clamped inverter

A new space vector modulation method for common-mode voltage reduction in four-level nested neutral point clamped (NNPC) inverter is proposed in this paper. The proposed method employs switching states with minimal absolute common-mode voltages to synthesize given reference vectors. A variety of vir...

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Bibliographic Details
Main Authors: Kai Tian, Bin Wu, Narimani, Mehdi, Dewei Xu, Zhongyuan Cheng, Zargari, Navid Reza
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
common-mode voltage reduction
dead-time effect
Inverters
Modulation
Nested neutral point clamped inverter
Power harmonic filters
Power transformer insulation
space vector modulation
Switches
Vectors
virtual vector
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Description
Summary:A new space vector modulation method for common-mode voltage reduction in four-level nested neutral point clamped (NNPC) inverter is proposed in this paper. The proposed method employs switching states with minimal absolute common-mode voltages to synthesize given reference vectors. A variety of virtual vectors are constructed to facilitate the synthesis. The effect of dead time on common-mode voltage reduction is analyzed. Appropriate switching sequences are designed to avoid the effect. With the proposed method, the common-mode voltage of the inverter is reduced to 1/18 of dc-link voltage, 80% off compared with sinusoidal pulse width modulation (SPWM) and conventional space vector modulation (C-SVM), which contributes to the design of transformer-less medium voltage (MV) power conversion and drives. The proposed method is verified by simulation results.
ISSN:1553-572X
DOI:10.1109/IECON.2014.7049187