A highly manufacturable 0.25 /spl mu/m multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology

A multiple-Vt high performance, high density and highly manufacturable 0.25 μm CMOS technology with a shallow trench isolation process has been successfully developed. Five metal layers with oxide CMP planarization, etchback W plug for borderless contacts/vias, and fully stacked contact/vias were us...

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Main Authors: Chang, M.H., Ting, J.K., Shy, J.S., Chen, L., Liu, C.W., Wu, J.Y., Pan, K.H., Hou, C.S., Tu, C.C., Chen, Y.H., Sue, S.L., Jang, S.M., Yang, S.C., Tsai, C.S., Chen, C.H., Tao, H.J., Tsai, C.C., Hsieh, H.C., Wang, Y.Y., Chang, R.Y., Cheng, K.B., Chu, T.Y., Yen, T.N., Wang, P.S., Weng, J.W., Hsu, J.H., Ho, Y.S., Ho, C.H., Huang, Y.C., Shiue, R.Y., Liew, B.K., Yu, C.H., Sun, S.C., Sun, J.Y.C.
Format: Conference Proceeding
Language:English
Subjects:
CMOS integrated circuits
CMOS logic circuits
CMOS process
CMOS technology
Etching
Foundries
Implants
Isolation technology
Manufacturing processes
Voltage
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Summary:A multiple-Vt high performance, high density and highly manufacturable 0.25 μm CMOS technology with a shallow trench isolation process has been successfully developed. Five metal layers with oxide CMP planarization, etchback W plug for borderless contacts/vias, and fully stacked contact/vias were used. Dual gate oxide process (5 nm for 2.5 V core, and 7 nm for 3.3 V I/O or 13 nm for 5 V I/O) with low defect density, and low Vt (∼0.2 V) or native Vt (∼0 V) devices for low power and mixed-mode applications are all demonstrated in this technology.
DOI:10.1109/VLSIT.1998.689236