Improved performance and resource usage of FPGA using resource-aware design; the case of a decimal array multiplier

Awareness of the available resources in FPGA platform can improve the quality of the hardware design. Decimal array multipliers due to their regular nature and compatibility with the CLB structure of FPGA platform are suitable cases to this aim. In this paper, PPG unit of a decimal multiplier has be...

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Bibliographic Details
Main Authors: Hosseiny, Adel, Amanollahi, Saba, Hashemi, Reza, Jahanian, Ali
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Arrays
Computers
Decimal Array Multiplier
Delays
Field programmable gate arrays
FPGA
Hardware
Resource-aware design
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Summary:Awareness of the available resources in FPGA platform can improve the quality of the hardware design. Decimal array multipliers due to their regular nature and compatibility with the CLB structure of FPGA platform are suitable cases to this aim. In this paper, PPG unit of a decimal multiplier has been realized using two different approaches in order to improve utilization of the FPGA resources.
ISSN:2325-9361
DOI:10.1109/CADS.2013.6714248