A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS

A 410 MS/s 2x interleaved 11bit pipelined SAR ADC in 28nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR and includes an on-chip calibration engine that detects and corrects comparator offsets and amplifier gain errors in the ba...

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Bibliographic Details
Main Authors: Verbruggen, Bob, Iriguchi, Masao, de la Guia Solaz, Manuel, Glorieux, Guy, Deguchi, Kazuaki, Malki, Badr, Craninckx, Jan
Format: Conference Proceeding
Language:English
Subjects:
Calibration
Clocks
CMOS integrated circuits
Engines
Gain
Histograms
pipelined SAR
Redundancy
Online Access:Request full text
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Summary:A 410 MS/s 2x interleaved 11bit pipelined SAR ADC in 28nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR and includes an on-chip calibration engine that detects and corrects comparator offsets and amplifier gain errors in the background. The ADC achieves a peak SNDR of 59.8 dB at 410 MS/s for an energy per conversion step of 6.5 fJ.
ISSN:2158-5601
2158-5636