Floating Point Architecture Extensions for Optimized Matrix Factorization

This paper examines the mapping of algorithms encountered when solving dense linear systems and linear least-squares problems to a custom Linear Algebra Processor. Specifically, the focus is on Cholesky, LU (with partial pivoting), and QR factorizations. As part of the study, we expose the benefits...

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Bibliographic Details
Main Authors: Pedram, A., Gerstlauer, A., van de Geijn, R. A.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Complexity theory
Computer architecture
floating point
linear algebra
low power
Matrix decomposition
matrix factorization
Registers
Vectors
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Summary:This paper examines the mapping of algorithms encountered when solving dense linear systems and linear least-squares problems to a custom Linear Algebra Processor. Specifically, the focus is on Cholesky, LU (with partial pivoting), and QR factorizations. As part of the study, we expose the benefits of redesigning floating point units and their surrounding data-paths to support these complicated operations. We show how adding moderate complexity to the architecture greatly alleviates complexities in the algorithm. We study design trade-offs and the effectiveness of architectural modifications to demonstrate that we can improve power and performance efficiency to a level that can otherwise only be expected of full-custom ASIC designs. A feasibility study shows that our extensions to the MAC units can double the speed of required vector-norm operations while reducing energy by 60%. Similarly, up to 20% speedup with 15% savings in energy can be achieved for LU factorization. We show how such efficiency is maintained even in the complex inner kernels of these operations.
ISSN:1063-6889
DOI:10.1109/ARITH.2013.21