A 60GHz power amplifier using high common-mode rejection technique

This paper proposes the method of realization of high common-mode rejection ratio(CMRR) at 60 GHz. High CMRR can compensate the differential mismatch. In the proposed method, virtual ground for differential-mode and LC peaking for common-mode are utilized. To confirm the effect of this technique, th...

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Bibliographic Details
Main Authors: Minami, R., Bunsen, K., Okada, K., Matsuzawa, A.
Format: Conference Proceeding
Language:English
Subjects:
60GHz
Capacitance
CMOS
CMOS integrated circuits
CMOS process
CMRR
Gain
Impedance
Power amplifiers
Power transmission lines
Radio frequency
Online Access:Request full text
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Summary:This paper proposes the method of realization of high common-mode rejection ratio(CMRR) at 60 GHz. High CMRR can compensate the differential mismatch. In the proposed method, virtual ground for differential-mode and LC peaking for common-mode are utilized. To confirm the effect of this technique, the 2-stage differential power amplifier is fabricated in a 65nm CMOS process. It achieves a CMRR of 26 dB, a power gain of 12.1 dB, a peak PAE of 11.1%, a P sat of 9.0 dBm, a power consumption of 45.8mW from a 1.0V power supply.
ISSN:2165-4727
2165-4743
DOI:10.1109/APMC.2012.6421481