Design of a real-time FPGA-based DAQ architecture for the LabPET II, an APD-based scanner dedicated to small animal PET imaging

To achieve submillimetric spatial resolution, a new detection block has been designed for the LabPET II, a small animal PET scanner being developed at Université de Sherbrooke. Each detection block consists of 2 arrays of 4×8 avalanche photodiodes (APD) individually coupled to an 8×8 scintillator a...

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Bibliographic Details
Main Authors: Njejimana, L., Tetrault, M., Arpin, L., Burghgraeve, A., Maille, P., Lavoie, J., Paulin, C., Koua, K. C., Bouziri, H., Panier, S., Ben Attouch, Mohamed W., Abidi, M., Pratte, J., Lecomte, R., Fontaine, R.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Computer architecture
Data acquisition
Engines
Positron emission tomography
Real-time systems
Timing
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Summary:To achieve submillimetric spatial resolution, a new detection block has been designed for the LabPET II, a small animal PET scanner being developed at Université de Sherbrooke. Each detection block consists of 2 arrays of 4×8 avalanche photodiodes (APD) individually coupled to an 8×8 scintillator array, to form 64 independent and parallel DAQ channels. This new detection block entails an 8-fold increase in pixel density compared to the LabPET™ I. A 64-channel mixed-signal Application Specified Integrated Circuit (ASIC) was designed to extract relevant PET data in real time from the LabPET II detection blocks. The ASIC is expected to support up to 3000 PET events/sec per channel. In order to interface the ASICs forming the PET camera with the storage units, a real-time FPGA-based digital DAQ system was designed. The DAQ system allows event harvesting, processing and transmission to a distant computer for image reconstruction as well as system programming and calibration. Real-time event processing embedded in the DAQ includes energy computation using a time-over-threshold (TOT) conversion scheme, timing corrections and event sorting trees. A real-time coincidence engine analyzes events and only keeps relevant information to minimize data throughput and post-acquisition data processing. The architecture consists of 3 layers of FPGA-based electronics wired through gigabit links: a Front-End board extracts timing and energy along with a pixel address, a Hub board sorts incoming events chronologically and a Coincidence board matches coincident events and copes with randoms estimation. Every FPGA in the different layers is accessible through an Ethernet link. The real-time digital architecture sustains the required throughput of ~111 Mevents/s for a ~37000 channels scanner configuration.
DOI:10.1109/RTC.2012.6418200