Future scaling of processor-memory interfaces

Continuous evolution in process technology brings energy-efficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high bandwidth and capacity, global wires improve slowly, and more cells are susceptible to hard and soft errors. Recently, the...

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Bibliographic Details
Main Authors: Ahn, Jung Ho, Jouppi, Norman P., Kozyrakis, Christos, Leverich, Jacob, Schreiber, Robert S.
Format: Conference Proceeding
Language:English
Subjects:
Hardware
Hardware > Integrated circuits > Interconnect
Hardware > Integrated circuits > Semiconductor memory
Hardware > Robustness
Online Access:Request full text
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Summary:Continuous evolution in process technology brings energy-efficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high bandwidth and capacity, global wires improve slowly, and more cells are susceptible to hard and soft errors. Recently, there are proposals aiming at better main-memory energy efficiency by dividing a memory rank into subsets. We holistically assess the effectiveness of rank subsetting in the context of system-wide performance, energy-efficiency, and reliability perspectives. We identify the impact of rank subsetting on memory power and processor performance analytically, then verify the analyses by simulating a chipmultiprocessor system using multithreaded and consolidated workloads. We extend the design of Multicore DIMM, one proposal embodying rank subsetting, for high-reliability systems and show that compared with conventional chipkill approaches, it can lead to much higher system-level energy efficiency and performance at the cost of additional DRAM devices.
ISSN:2167-4329
2167-4337
DOI:10.1145/1654059.1654102