A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization

This paper introduces MDAC equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain and settling errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sa...

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Bibliographic Details
Main Authors: Jiangfeng Wu, Chun-Ying Chen, Tianwei Li, Wenbo Liu, Lin He, Tsai, Shauhyuarn Sean, Binning Chen, Chun-Sheng Huang, Juo-Jung Hung, Wei-Ta Shih, Hing Hung, Jaffe, S., Tan, L., Hung Vu
Format: Conference Proceeding
Language:English
Subjects:
Accuracy
Bandwidth
Calibration
CMOS integrated circuits
Equalizers
Finite impulse response filter
Pipelines
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Summary:This paper introduces MDAC equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain and settling errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sampling frequency, thereby reducing ADC power. MDAC equalization is demonstrated in a 240mW 2.1GS/s 12b ping-pong pipeline ADC in 40nm CMOS where MDAC RA power is reduced from 175mW to 53mW by 70%.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2012.6330654