Transition delay fault testing of 3D ICs with IR-drop study

In order to ensure the correctness of 3D ICs, they need to be tested both before and after their individual dies are bonded. All previous works in the area of 3D IC testing consider only stuck-at fault testing. However, 3D ICs also need to be tested for delay defects. In this work, we present a tran...

Full description

Saved in:
Bibliographic Details
Main Authors: Panth, S., Sung Kyu Lim
Format: Conference Proceeding
Language:English
Subjects:
Automatic test pattern generation
Clocks
Educational institutions
Logic gates
Registers
Through-silicon vias
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In order to ensure the correctness of 3D ICs, they need to be tested both before and after their individual dies are bonded. All previous works in the area of 3D IC testing consider only stuck-at fault testing. However, 3D ICs also need to be tested for delay defects. In this work, we present a transition delay test infrastructure that can be used to test a 3D IC both before and after bonding. Furthermore, we present a methodology to test the through silicon vias (TSVs) after bonding, without necessitating regeneration of test patterns. Results show that the overhead involved is negligible. In addition, at-speed testing of circuits can suffer from large IR drop problems. In this paper, we also study the IR drop of 3D ICs during transition delay fault testing. We study how different configurations of probe pads affect the pre-bond IR drop. We also study how this IR drop changes from the pre-bond to the post-bond case.
ISSN:1093-0167
2375-1053
DOI:10.1109/VTS.2012.6231065