A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and...

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Main Authors: Harwood, M., Nielsen, S., Szczepanek, A., Allred, R., Batty, S., Case, M., Forey, S., Gopalakrishnan, K., Kan, L., Killips, B., Mishra, P., Pande, R., Rategh, H., Ren, A., Sanders, J., Schoy, A., Ward, R., Wetterhorn, M., Yeung, N.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS integrated circuits
Equalizers
Finite impulse response filter
Optical transmitters
Receivers
Regulators
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Summary:A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches . This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2012.6177032