Signal transition structure optimization for 16 Gbps SFP cage and PCB interface

SFP (Small Form-factor Pluggable) module and SFP cage form an interface between a network device and an optic cable or a copper cable for data communication and telecommunication. Data rate on such an interface for a high-speed channel varies from 1 Gbps (Gigabit per second) to 10 Gbps for the exist...

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Bibliographic Details
Main Authors: Jianmin Zhang, Hanfeng Wang, Lim, J., Qiu, K., Brooks, R., Chen, B.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Cavity resonators
Impedance
Insertion loss
Optimization
Pins
Resonant frequency
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Summary:SFP (Small Form-factor Pluggable) module and SFP cage form an interface between a network device and an optic cable or a copper cable for data communication and telecommunication. Data rate on such an interface for a high-speed channel varies from 1 Gbps (Gigabit per second) to 10 Gbps for the existing products, and products with the data rate of 16 Gbps are under development. Due to the differences of networking platform, data rate, and channel length, this interface can be directly driven by an ASIC (Application-Specific Integrated Circuit) or an EDC (Electric Dispersion Compensation) chip in electric domain. Compliance tests are enforced on the interface to fulfil the interoperability requirement, which makes the signal integrity work extremely challenge at 16 Gbps. Since the discontinuity on the interface of a PCB (Printed Circuit Board) and a SFP cage is dominant in the electric path, optimization such an interface structure is critical to meet the compliance specification and achieve system BER (Bit Error Rate). In this paper, a fast via tool is used initially for quick solution about the interface structure optimization. The optimized parameter is verified in a full-wave modelling, and the via structure related resonance is observed and identified. Based on the given SFP cage footprint and observed resonance, a new signal transition structure for the SFP cage and PCB interface is finally proposed, modelled and optimized.
ISSN:2158-110X
2158-1118
DOI:10.1109/ISEMC.2011.6038415