Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies

The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 μm and 90 nm CMOS. The efficie...

Full description

Saved in:
Bibliographic Details
Main Authors: Gyepes, G, Brenkus, J, Arbet, D, Stopjakova, V
Format: Conference Proceeding
Language:English
Subjects:
6-transistor cell
CMOS integrated circuits
dynamic supply current
iddt
Integrated circuit modeling
memory test
Monitoring
open defects
Random access memory
Resistance
Resistors
SRAM
Testing
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 μm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.
DOI:10.1109/DDECS.2011.5783118