Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application

A compact STT (Spin-Transfer Torque)-RAM with a 14F 2 cell was integrated using modified DRAM processes at the 54 nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through t...

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Main Authors: Suock Chung, Rho, K.-M, Kim, S.-D, Suh, H.-J, Kim, D.-J, Kim, H.-J, Lee, S.-H, Park, J.-H, Hwang, H.-M, Hwang, S.-M, Lee, J.-Y, An, Y.-B, Yi, J.-U, Seo, Y.-H, Jung, D.-H, Lee, M.-S, Cho, S.-H, Kim, J.-N, Park, G.-J, Gyuan Jin, Driskill-Smith, A, Nikitin, V, Ong, A, Tang, X, Yongki Kim, Rho, J.-S, Park, S.-K, Chung, S.-W, Jeong, J.-G, Hong, S.-J
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Magnetic tunneling
Microprocessors
Random access memory
Switches
Thermal stability
Transistors
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Summary:A compact STT (Spin-Transfer Torque)-RAM with a 14F 2 cell was integrated using modified DRAM processes at the 54 nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through the direct access capability and normal chip operation in our STT-RAM test blocks, the switching behavior of bit cell arrays was also analyzed statistically. From this data and from the scaling trend of STT-RAM, we estimate that the unit cell dimension below 30 nm can be smaller than 8F 2 .
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2010.5703351