Capacitorless 1T Memory Cells Using Channel Traps at Grain Boundaries

A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can b...

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Bibliographic Details
Published in:IEEE electron device letters 2010-10, Vol.31 (10), p.1125-1127
Main Authors: Yen-Ting Chen, Hung-Chang Sun, Ching-Fang Huang, Ting-Yun Wu, Liu, C W, Yuan-Jun Hsu, Jim-Shone Chen
Format: Article
Language:English
Subjects:
Applied sciences
Channel traps
Channels
Degradation
Design. Technologies. Operation analysis. Testing
Drains
Electronics
Exact sciences and technology
Extrapolation
Flash memory
Grain boundaries
Integrated circuits
Integrated circuits by function (including memories and processors)
Magnetic and optical mass memories
MOSFETs
Nonvolatile memory
poly-Si
Programming
Random access memory
Semiconductor devices
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
single-transistor (1T) random access memory (RAM)
Storage and reproduction of information
Sun
Thin film transistors
thin-film transistor (TFT)
Transistors
Tunneling
Windows (intervals)
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Summary:A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can be read by modulating the barrier height at the grain boundary. The extrapolated retention time at the half of the current window is ~10 7 s. There is no degradation after 2000 write/erase cycles by trap-assisted tunneling programming. The low-temperature process of the TFT cells is attractive for the 3-D integration.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2010.2057406