Reduction of the latch effect in SOI MOSFETS by the silicidation of the source

A simple physical model is developed to assess the effect on single transistor latch voltage of carrier lifetime reduction and emitter efficiency degradation. The model predicts the efficacy of the latter mechanism and this is achieved experimentally by silicidation of the source. This has the effec...

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Bibliographic Details
Published in:ESSDERC '91: 21st European Solid State Device Research Conference 1991, Vol.15 (1), p.203-206
Main Authors: McDaid, L.J., Hall, S., Eccleston, W., Alderman, J.C.
Format: Article
Language:English
Subjects:
Avalanche breakdown
Bipolar transistor circuits
Breakdown voltage
Degradation
Latches
Leakage current
MOSFETs
Predictive models
Semiconductor device modeling
Silicidation
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Summary:A simple physical model is developed to assess the effect on single transistor latch voltage of carrier lifetime reduction and emitter efficiency degradation. The model predicts the efficacy of the latter mechanism and this is achieved experimentally by silicidation of the source. This has the effect of effectively placing the source ohmic contact close to the source/body metallurgical junction thus enhancing the hole component of the total current across the junction thereby reducing the emitter efficiency. In comparison to a non-silicided source, a 20% increase in breakdown voltage is achieved. Silicidation of both the source and drain regions is performed simultaneously thus maintaining device symmetry and simplicity of processing. No significant degradation of drain leakage current was observed.
ISSN:0167-9317
1873-5568
DOI:10.1016/0167-9317(91)90213-W