A 550 MHz 9.3 mW CMOS frequency divider

This paper deals with the design of a high speed CMOS programmable frequency counter design. It is the heart of a frequency synthesizer IC. By using an end-of-count (EOC) detecting algorithm, and a modified ripple down counter, we designed a high performance 14-bits programmable counter. The program...

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Bibliographic Details
Main Authors: Jiin-Chuan Wu, Hun-Hsien Chang
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
CMOS technology
Counting circuits
Frequency conversion
Frequency synthesizers
Heart
Integrated circuit synthesis
Power measurement
Power supplies
Voltage
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Summary:This paper deals with the design of a high speed CMOS programmable frequency counter design. It is the heart of a frequency synthesizer IC. By using an end-of-count (EOC) detecting algorithm, and a modified ripple down counter, we designed a high performance 14-bits programmable counter. The programming values N can be from 3 to 16384. The chip is implemented in 0.8 /spl mu/m CMOS technology, active area die size is 440 /spl mu/m/spl times/510 /spl mu/m. The counter was measured to operate at 550 MHz with 5V power supply voltage, 317 MHz with 3V power supply voltage, and 135 MHz with 2V power supply voltage. It can be used to design frequency synthesizer ICs for radio communication products.
DOI:10.1109/ISCAS.1995.521485