Single-Electron-Based Flexible Multivalued Exclusive-or Logic Gate

By using two symmetrical sidewall gates, we implemented a Si-based single-electron exclusive- OR (XOR) gate and reported on the first flexible multivalued (MV) functionality. A grayscale contour plot of the output voltages displays alternating high/low values as a function of two single-electron tra...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on electron devices 2009-05, Vol.56 (5), p.1048-1055
Main Authors: KIM, Sang-Jin, LEE, Chang-Keun, CHUNG, Rae-Sik, PARK, Eun-Sil, SHIN, Seung-Jun, CHOI, Jung-Bum, YU, Yun-Seop, KIM, Nam-Soo, HYUNG GYOO LEE, PARK, Keun-Hyung
Format: Article
Language:English
Subjects:
Applied sciences
Arithmetic
Circuit properties
CMOS integrated circuits
Coulomb blockade
Data mining
Digital circuits
Displays
Electric potential
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
exclusive-OR (XOR) gate
FETs
Gates
Logic
Logic gates
Molecular electronics, nanoelectronics
MOSFETs
multivalued (MV) logic
Oscillators
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Shape
Si-based single-electron transistor (SET)
Single-electron transistors
Transistors
Voltage
Voltage measurement
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:By using two symmetrical sidewall gates, we implemented a Si-based single-electron exclusive- OR (XOR) gate and reported on the first flexible multivalued (MV) functionality. A grayscale contour plot of the output voltages displays alternating high/low values as a function of two single-electron transistor (SET) input voltages. Their voltage transfer characteristics display typical XOR or XNOR gate function depending on input voltages for binary, MV, and binary-MV mixed-modes. This flexible two-input XOR gate, combined with the previously reported NAND/NOR gates, provide three basic arithmetic blocks for the SET-based MV logic gate family.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2009.2016399