External DDR2-constrained NOC-based 24-processors MPSOC design and implementation on single FPGA

Network on chip (NOC) has been proposed for the connection substrate of multiprocessor system on chip (SoC) due to limited bandwidth of bus based solutions. Although some designs are emerging actual design experiences of NOC based multiprocessor system on chip remain scarce contrary to simulation ba...

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Bibliographic Details
Main Authors: Zhoukun Wang, Hammami, O.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Computer architecture
Field programmable gate arrays
Libraries
Multiprocessing systems
Network-on-a-chip
Pins
Prototypes
System-on-a-chip
Telecommunication network reliability
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Description
Summary:Network on chip (NOC) has been proposed for the connection substrate of multiprocessor system on chip (SoC) due to limited bandwidth of bus based solutions. Although some designs are emerging actual design experiences of NOC based multiprocessor system on chip remain scarce contrary to simulation based studies. However, implementation constraints clearly affects th design and modelling of a complex multiprocessor. In this paper we present the design and implementation of a 24-processors multiprocessor system with 24 processors under the constraints of limited access to 4 external DDR2 memory banks. All the processors and DDR2 memories are connected to a network on chip through open core protocol (OCP) interface. Multiple clock domains result ing from various IP complexities requires global asynchronous local synchronous (GALS) design methodlogy which adds some extra area. The multiprocessor system is fully implemented on Xilinx Virtex-4 FX140 FPGA based board and uses about 90 % of the chip area.
ISSN:2162-0601
2162-061X
DOI:10.1109/IDT.2008.4802495