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Development of very high rate and resolution neutron detectors with novel readout and DAQ hard- and software in DETNI

In the Joint Research Activity DETNI (DETectors for Neutron Instrumentation) of the FP6 EU Integrated Infrastructure Initiative for Neutron Scattering and Muon Spectroscopy (NMI3) prototypes of three novel modular thermal neutron area detector types, based on thin solid neutron converters, were buil...

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Main Authors: Alimov, S. S., Borga, A., Brogna, A., Buzzetti, S., Casinini, F., Dabrowski, W., Fiutowski, T., Gebauer, B., Kemmerling, G., Klein, M., Mindur, B., Modzel, G., Petrillo, C., Sacchetti, F., Schmidt, C. J., Soltveit, H. K., Solvag, K. S., Szczygiel, R., Schulz, C., Thielmann, C., Trunk, U., Wiacek, P., Wilpert, T.
Format: Conference Proceeding
Language:English
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Summary:In the Joint Research Activity DETNI (DETectors for Neutron Instrumentation) of the FP6 EU Integrated Infrastructure Initiative for Neutron Scattering and Muon Spectroscopy (NMI3) prototypes of three novel modular thermal neutron area detector types, based on thin solid neutron converters, were built and tested, which were developed for time- and wavelength resolved neutron detection with 2-D spatial and time resolutions of 50-1000 µm (FWHM) and of up to 2 ns, respectively, and for counting rates in the 10 7 - 10 8 cps range, i.e. for coping with the highest resolution and rate requirements at pulsed spallation neutron sources with MW average proton beam power like ESS. The detector types are (i) four-fold segmented modules of Silicon microstrip detectors (Si-MSD) with 157 Gd converter layer between two double-sided Si sensors with 80 ¼m strip pitch, (ii) hybrid low-pressure microstrip gas chamber (MSGC) detectors with three-stage gas amplification and 2-D position-sensitive MSGC plates either side of a composite 157 Gd/CsI converter, (iii) CASCADE detectors with cascaded 10 B-coated GEM (Gas Electron Multiplier) foils either side of a 2-D position-sensitive readout electrode. For readout in DETNI prototypes of two novel, channel-wise self-triggered high-rate ASICs, of ADC-FPGA boards with Gigabit glass fiber readout and of the necessary data acquisition firmware and software have been developed. The ASICs, i.e. the 128-channel n-XYTER ASIC, optimized for the Si-MSD and strip hit rates of 200 khits/s, and the 32-channel MSGCROC ASIC for the MSGC with variable amplification and strip rates of 900 khits/s, deliver for each strip spatial and 4 (2) ns time stamp resolution, respectively, the latter e.g. for correlating x and y strips unambiguously, as well as analog amplitude resolution for center-of-gravity interpolation and gating. In this paper the current status of prototyping will be reported.
ISSN:1082-3654
2577-0829
DOI:10.1109/NSSMIC.2008.4774759