A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm

In the diverse world of NAND flash applications, higher storage capacity is not the only imperative. Increasingly, performance is a differentiating factor and is also a way of creating new markets or expanding existing markets. While conventional memory uses, for actual operations, every other cell...

Full description

Saved in:
Bibliographic Details
Main Authors: Cernea, Raul, Pham, Long, Moogat, Farookh, Chan, Siu, Le, Binh, Li, Yan, Tsao, Shouchang, Tseng, Tai-Yuan, Nguyen, Khanh, Li, Jason, Hu, Jayson, Park, Jong, Hsu, Cynthia, Zhang, Fanglin, Kamei, Teruhiko, Nasu, Hiroaki, Kliza, Phil, Htoo, Khin, Lutze, Jeffrey, Dong, Yingda, Higashitani, Masaaki, Yang, Junhui, Lin, Hung-Szu, Sakhamuri, Vamshi, Li, Alan, Pan, Feng, Yadala, Sridhar, Taigor, Subodh, Pradhan, Kishan, Lan, James, Chan, James, Abe, Takumi, Fukuda, Yasuyuki, Mukai, Hideo, Kawakami, Koichi, Liang, Connie, Ip, Tommy, Chang, Shu-Fen, Lakshmipathi, Jaggi, Huynh, Sharon, Pantelakis, Dimitris, Mofidi, Mehrdad, Quader, Khandker
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Decoding
Diodes
Latches
Logic
MOS devices
MOSFETs
Nonvolatile memory
Switches
Voltage
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In the diverse world of NAND flash applications, higher storage capacity is not the only imperative. Increasingly, performance is a differentiating factor and is also a way of creating new markets or expanding existing markets. While conventional memory uses, for actual operations, every other cell along a selected word line (WL) (Takeuchi, 2006), this design simultaneously exercises them all. A performance improvement of at least 100% is derived from this all-bitline (ABL) architecture relative to conventional chips. Additional techniques push performance to even higher levels.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2008.4523236