Quasi-cyclic generalized ldpc codes with low error floors

In this paper, a novel methodology for designing structured generalized LDPC (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together w...

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Bibliographic Details
Published in:IEEE transactions on communications 2008-01, Vol.56 (1), p.49-57
Main Authors: Liva, G., Ryan, W.E., Chiani, M.
Format: Article
Language:English
Subjects:
Additive white noise
Applied sciences
Bipartite graph
Channels
Circuits
Coding, codes
Decoding
Design methodology
Doping
Errors
Exact sciences and technology
Floors
Gaussian
Graphs
Hamming codes
Information, signal and communications theory
Iterative decoding
Parity check codes
Quasi-doping
Signal and communications theory
Telecommunications and information theory
Turbo codes
Waterfalls
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Summary:In this paper, a novel methodology for designing structured generalized LDPC (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call LDPC code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.
ISSN:0090-6778
1558-0857
DOI:10.1109/TCOMM.2008.050600