Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications

This paper presents a radix-2 memory-based FFT processors, namely, MBFFTP, with a memory size of N words for large N complex points, where each word contains 24 bits. The developed MBFFTP meets DVB-T standard and can handle both 2K and 8K modes in the same architecture. The processors have been desi...

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Bibliographic Details
Main Authors: Chin-Long Wey, Wei-Chien Tang, Shin-Yo Lin
Format: Conference Proceeding
Language:English
Subjects:
Delay
Digital video broadcasting
Frequency conversion
Frequency estimation
Frequency synchronization
Memory architecture
OFDM
Random access memory
Standards development
Very large scale integration
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Summary:This paper presents a radix-2 memory-based FFT processors, namely, MBFFTP, with a memory size of N words for large N complex points, where each word contains 24 bits. The developed MBFFTP meets DVB-T standard and can handle both 2K and 8K modes in the same architecture. The processors have been designed and implemented in TSMC 0.18mum 1P6M process. Results show that simple MBFFTP achieves a maximum work frequency of 173MHz, where its core chip area is approximately 1.80 mm with a core power consumption of 40.80 mW at 55 MHz for 2K mode and 48.16 mW at 65 MHz for 8K mode.
ISSN:2159-3469
2159-3477
DOI:10.1109/ISVLSI.2007.43