An External Test Approach for Network-on-a-Chip Switches

Over the past few years, network-on-a-chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have...

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Bibliographic Details
Main Authors: Raik, J., Govind, V., Ubar, R.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Computer networks
Delay
Design for testability
Electronic mail
Hardware
Network-on-a-chip
Routing
Switches
System testing
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Summary:Over the past few years, network-on-a-chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on general purpose design-for-testability (DFT) approaches and there is a lack of test algorithms dedicated to on-chip networks. The main contribution of this paper is a well-scalable external test method, where insertion of wrappers and scan paths will not be required. The paper proposes an external test method for NoC based on functional fault models, which targets single stuck-at faults in the network switches. Furthermore, 100 per cent of delay faults open and shorts between adjacent interconnection lines are covered by the method. The approach allows reaching higher fault coverage in comparison to the recent DFT based solutions
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2006.260967