Power supply variation effects on timing characteristics of clocked registers

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (V DD ) on the timing characteristics of registers are investigated in this paper. The sensitivity of the setup time and data propagation de...

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Main Authors: Roberts, W.R., Velenis, D.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Clocks
Frequency
Power supplies
Propagation delay
Registers
Robustness
Timing
Uncertainty
Voltage
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Velenis, D.
description Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (V DD ) on the timing characteristics of registers are investigated in this paper. The sensitivity of the setup time and data propagation delay to power supply variations is demonstrated for four different register designs. Design modifications are proposed in order to enhance the robustness of each register design under V DD variations
doi_str_mv 10.1109/ISCAS.2006.1692630
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source IEEE Xplore All Conference Series
subjects Circuits
Clocks
Frequency
Power supplies
Propagation delay
Registers
Robustness
Timing
Uncertainty
Voltage
title Power supply variation effects on timing characteristics of clocked registers
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