Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes

Conventional iterative decoding with flooding or parallel schedule can be formulated as a fixed-point problem solved iteratively by a successive substitution (SS) method. In this paper, we investigate the dynamics of a continuous-time (asynchronous) analog implementation of iterative decoding, and s...

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Bibliographic Details
Published in:IEEE transactions on communications 2006-01, Vol.54 (1), p.61-70
Main Authors: Hemati, S., Banihashemi, A.H.
Format: Article
Language:English
Subjects:
Algorithms
Analog circuits
Analog decoding
Applied sciences
Asymptotic properties
asynchronous iterative methods
Belief propagation
belief propagation (BP)
Code standards
Codes
Coding, codes
Decoders
Decoding
Dynamic tests
Dynamics
dynamics of iterative decoding
Exact sciences and technology
Floods
Gaussian distribution
Information, signal and communications theory
Iterative algorithms
Iterative decoding
Iterative methods
low-density parity-check (LDPC) codes
Mathematical models
min-sum (MS)
Parity check codes
Performance analysis
Signal and communications theory
Steady-state
Strontium
Studies
successive relaxation (SR)
successive substitution (SS)
sum-product
Telecommunications and information theory
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Summary:Conventional iterative decoding with flooding or parallel schedule can be formulated as a fixed-point problem solved iteratively by a successive substitution (SS) method. In this paper, we investigate the dynamics of a continuous-time (asynchronous) analog implementation of iterative decoding, and show that it can be approximated as the application of the well-known successive relaxation (SR) method for solving the fixed-point problem. We observe that SR with the optimal relaxation factor can considerably improve the error-rate performance of iterative decoding for short low-density parity-check (LDPC) codes, compared with SS. Our simulation results for the application of SR to belief propagation (sum-product) and min-sum algorithms demonstrate improvements of up to about 0.7 dB over the standard SS for randomly constructed LDPC codes. The improvement in performance increases with the maximum number of iterations, and by accordingly reducing the relaxation factor. The asymptotic result, corresponding to an infinite maximum number of iterations and infinitesimal relaxation factor, represents the steady-state performance of analog iterative decoding. This means that under ideal circumstances, continuous-time (asynchronous) analog decoders can outperform their discrete-time (synchronous) digital counterparts by a large margin. Our results also indicate that with the assumption of a truncated Gaussian distribution for the random delays among computational modules, the error-rate performance of the analog decoder, particularly in steady state, is rather independent of the variance of the distribution. The proposed simple model for analog decoding, and the associated performance curves, can be used as an "ideal analog decoder" benchmark for performance evaluation of analog decoding circuits.
ISSN:0090-6778
1558-0857
DOI:10.1109/TCOMM.2005.861668