Design of FFT processor with low power complex multiplier for OFDM-based high-speed wireless applications

We introduce a fixed-point 16-bit 64-point FFT processor for OFDM-based wireless applications. The processor is based on decimation-in-time (DIT) radix-2 butterfly FFT algorithm. The canonical signed digit is used to implement constant complex multiplications with carry save add (CSA) tree for lower...

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Bibliographic Details
Main Authors: Min Jiang, Bing Yang, Yiling Fu, Anping Jiang, Xin-an Wang, Xuewen Gan, Baoying Zhao, Tianyi Zhang
Format: Conference Proceeding
Language:English
Subjects:
Amplitude modulation
Computational modeling
Computer architecture
Discrete Fourier transforms
Energy consumption
Hardware
Intensity modulation
Phase modulation
Process design
Quadrature amplitude modulation
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Summary:We introduce a fixed-point 16-bit 64-point FFT processor for OFDM-based wireless applications. The processor is based on decimation-in-time (DIT) radix-2 butterfly FFT algorithm. The canonical signed digit is used to implement constant complex multiplications with carry save add (CSA) tree for lower power and cost. The simulation shows the module can reach low cost/power and high speed for OFDM-based high-speed wireless applications.
DOI:10.1109/ISCIT.2004.1413792