A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges

A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage. A new DAC architecture presents the benefits of a differential approach while sampling single-ended signals. Thanks to new low power design solutions in...

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Bibliographic Details
Main Authors: Confalonleri, P., Zarnprogno, M., Girardi, F., Nicollini, G., Nagari, A.
Format: Conference Proceeding
Language:English
Subjects:
Analog-digital conversion
Capacitors
Cellular phones
Circuits
Clocks
CMOS process
Energy consumption
Sampling methods
Signal sampling
Voltage
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Summary:A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage. A new DAC architecture presents the benefits of a differential approach while sampling single-ended signals. Thanks to new low power design solutions in the ADC comparator and the built-in reference buffer, the total ADC power consumption is only 2.7 mW at 2.4 V supply and 1 MSps. The active area is 0.4 mm/sup 2/ in a 0.35 /spl mu/m CMOS process.
DOI:10.1109/ESSCIR.2004.1356666