A high-frequency decimal multiplier

Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decimal data. This paper presents an iterative decimal multiplier, which operates at high clock frequencies and scales well to...

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Bibliographic Details
Main Authors: Kenney, R.D., Schulte, M.J., Erle, M.A.
Format: Conference Proceeding
Language:English
Subjects:
Application software
Applied sciences
Business
Circuit properties
Clocks
Delay estimation
Design. Technologies. Operation analysis. Testing
DH-HEMTs
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Floating-point arithmetic
Frequency
Integrated circuits
Internet
Libraries
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
USA Councils
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Summary:Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decimal data. This paper presents an iterative decimal multiplier, which operates at high clock frequencies and scales well to large operand sizes. The multiplier uses a new decimal representation for intermediate products, which allows for a very fast two-stage iterative multiplier design. Decimal multipliers, which are synthesized using a 0.11 micron CMOS standard cell library, operate at clock frequencies close to 2 GHz. The latency of the proposed design to multiply two n-digit BCD operands is (n+8) cycles with a new multiplication able to begin every (n+1) cycles.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2004.1347893