SVX4: a new deep-submicron readout IC for the Tevatron collider at Fermilab

SVX4 is the new silicon strip readout IC designed to meet the increased radiation tolerance requirements for Run IIb at the Tevatron collider. Devices have been fabricated, tested, and approved for production. The SVX4 design is a technology migration of the SVX3D design currently in use by CDF. Whe...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2004-10, Vol.51 (5), p.1968-1973
Main Authors: Krieger, B., Alfonsi, S., Bacchetta, N., Centro, S., Christofek, L., Garcia-Sciveres, M., Haber, C., Hanagaki, K., Hoff, J., Johnson, M., von der Lippe, H., Lujan, P., Mandelli, E., Meng, G., Nomerotski, A., Pellet, D., Rapidis, P., Utes, M., Walder, J.-P., Weber, M., Wester, W., Wilkes, T., Yarema, R., Yao, W., Zimmerman, T.
Format: Article
Language:English
Subjects:
Capacitance
CMOS process
CMOS technology
Collaboration
Integrated circuit noise
Particle accelerators
Production
Silicon
Strips
Testing
Topology
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Summary:SVX4 is the new silicon strip readout IC designed to meet the increased radiation tolerance requirements for Run IIb at the Tevatron collider. Devices have been fabricated, tested, and approved for production. The SVX4 design is a technology migration of the SVX3D design currently in use by CDF. Whereas SVX3D was fabricated in a 0.8-/spl mu/m radiation-hard process, SVX4 was fabricated in a standard 0.25-/spl mu/m mixed-signal CMOS technology using the "radiation tolerant by design" transistor topologies devised by the CERN RD49 collaboration. The specific cell layouts include digital cells developed by the ATLAS Pixel group, and full-custom analog blocks. Unlike its predecessors, the new design also includes the necessary features required for generic use by both the CDF and D0 experiments at Fermilab. Performance of the IC includes >20 MRad total dose tolerance, and /spl sim/2000 e-rms equivalent input noise charge with 40-pF input capacitance, when sampled at 132-ns period with an 80-ns preamp risetime. At the nominal digitize/readout rate of 106/53 MHz, the 9 mm/spl times/6.3 mm die dissipates /spl sim/2 mW/channel average at 2.5 V. A review of typical operation, details of the design conversion process, and performance measurements are covered.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2004.836027