Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

The polyphase channelizer is an important component of a subband adaptive filtering system. This paper presents an efficient hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer, integrating optimizations at algorithmic, architectural and circuit level....

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Bibliographic Details
Main Authors: Yongtao Wang, Mahmoodi, H., Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Roy, K.
Format: Conference Proceeding
Language:English
Subjects:
Adaptive filters
Applied sciences
Circuits
Computational complexity
Computational modeling
Computer architecture
Detection, estimation, filtering, equalization, prediction
Exact sciences and technology
Flip-flops
Hardware
Information, signal and communications theory
Miscellaneous
Power system modeling
Signal and communications theory
Signal processing
Signal, noise
System performance
Systems, networks and services of telecommunications
Telecommunications
Telecommunications and information theory
Transmission and modulation (techniques and equipments)
Very large scale integration
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Summary:The polyphase channelizer is an important component of a subband adaptive filtering system. This paper presents an efficient hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer, integrating optimizations at algorithmic, architectural and circuit level. At the algorithm level, a computationally efficient structure is derived. Tradeoffs between hardware complexity and system performance are explored during the fixed-point modeling of the system. A computational complexity reduction technique is also employed to reduce the complexity of the hardware architecture. Circuit-level optimizations, including an efficient commutator implementation, dual-VDD scheme and novel level-converting flip-flops, are also integrated. Simulation results show that the design consumes 352 mW power with system throughput of 480 million samples per second (MSPS). A test chip has been submitted for fabrication to validate the proposed hardware architecture and VLSI design techniques.
ISSN:1520-6149
2379-190X
DOI:10.1109/ICASSP.2004.1327056