Breakthrough Processes for Si CMOS Devices with BEOL Compatibility for 3D Sequential Integrated more than Moore Analog Applications

This work unlocks Low Temperature (LT) technological showstoppers in view of versatile analog high voltage (> 2.5\mathrm{V}) BEOL (400°C) devices. We demonstrated monocrystalline Silicon (mono-Si) devices with CMOS-compatible poly gate thanks to Nanosecond Laser Annealing (NLA) in melt regime and...

Full description

Saved in:
Bibliographic Details
Main Authors: Bosch, D., Viey, A., Frutuoso, T. Mota, Lheritier, P., Licitra, C., Zerhouni, N., Albouy, A., Brunet, L., Magalhaes-Lucas, A., da Silva, L. M. B., Boutry, H., Fahmy Taha Abdelrahman, M. Husien, Cristiano, F., Gassilloud, R., Ribotta, M., Romano, G., Vandendaele, W., Benevent, V., Opprecht, M., Kerdiles, S., Milesi, F., Mazen, F., Sklenard, B., Euvrard-Colnat, C., Sturm, J., Lambert, A., Candebage, C., Laraignou, L., Boulard, F., Sarrazin, A., De Souza, M., Theodorou, C., Garros, X., Batude, P.
Format: Conference Proceeding
Language:English
Subjects:
Annealing
CMOS technology
Logic gates
Performance evaluation
Semiconductor lasers
Three-dimensional displays
Very large scale integration
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This work unlocks Low Temperature (LT) technological showstoppers in view of versatile analog high voltage (> 2.5\mathrm{V}) BEOL (400°C) devices. We demonstrated monocrystalline Silicon (mono-Si) devices with CMOS-compatible poly gate thanks to Nanosecond Laser Annealing (NLA) in melt regime and junction dopants activation without diffusion at 400°C to preserve the engineered junction profile. HPD2 final anneal cures LT gate stack, achieving performances in line with planar analog CMOS technology: D it =\text{le}11\text{cm}^{2}.\text{eV}^{-1},\mathrm{N}_{\mathrm{t}} \leq 1 e17 \text{eV}^{-1}.\text{cm}^{-3}\mu_{\text{pMOS}} =179\text{cm}^{2}.\mathrm{V}^{-1}.\mathrm{s}^{-1}\mu_{\mathrm{n}\text{MOS}}=505\text{cm}^{2}.\mathrm{V}^{-1}.\mathrm{s}^{-1} .
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631398