Cell to Core-Periphery Overlap (C2O) Based on BCAT for Next Generation DRAM

The ongoing trend of DRAM design rule scaling has faced with serious challenges. This paper focuses on sustaining the scaling momentum by introducing Cell to Core-Periphery Overlap (C20) based on Buried Channel Array Transistors (BCAT). This approach enables bit growth and bit cost reduction with le...

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Main Authors: Lee, Kiseok, Lee, Hongjun, Choi, Hyungeun, Kim, Jeongsu, Kim, Kyunghwan, Jeong, Moonyoung, Bae, Soohyun, Kim, Hyebin, Lee, Jiyun, Kim, Minsoo, Kim, Keunnam, Kim, Huijung, Park, Sungmin, Park, Taejin, Han, Jin-woo, Oh, Jeonghoon, Kim, Yong Kwan, Yim, Sungsoo, Kim, Bongsoo, Park, Jemin, Song, Jaihyuk
Format: Conference Proceeding
Language:English
Subjects:
BCAT
Cell to Core-Periphery Overlap
Computer architecture
DRAM
Microprocessors
Random access memory
Sensors
Threshold voltage
Very large scale integration
Wafer bonding
Online Access:Request full text
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Summary:The ongoing trend of DRAM design rule scaling has faced with serious challenges. This paper focuses on sustaining the scaling momentum by introducing Cell to Core-Periphery Overlap (C20) based on Buried Channel Array Transistors (BCAT). This approach enables bit growth and bit cost reduction with less scaling and introducing wafer bonding technique. Moreover, by expanding the core area and reducing mismatch, we significantly enhance sensing characteristics, thereby relaxing the storage capacitance burden. Additionally, stress-induced experiments by the wafer bonding process demonstrate that these improvements do not adversely affect the performance of DRAM core-periphery transistors.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631320