A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process

Most digital transformer designs used non-overlapping coil topology, which increases the design area on silicon. This study demonstrates a digital transformer based on a multi-layer, over-lapping coil topology that increases the trans-former's mutual inductance. Two interwound coils composed of...

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Bibliographic Details
Main Authors: Jose, Oliver Lexter July A., Chang, Yun-Che, Kolakaluri, Venkata Naveen, Co, Celso B., Chou, Mitch Ming-Chi, Wang, Chua-Chin
Format: Conference Proceeding
Language:English
Subjects:
CMTI
Coils
coreless
Digital transformer
high-frequency
HV CMOS
Inductance
metal layers
Semiconductor device measurement
System-on-chip
Time measurement
Topology
Transformers
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Summary:Most digital transformer designs used non-overlapping coil topology, which increases the design area on silicon. This study demonstrates a digital transformer based on a multi-layer, over-lapping coil topology that increases the trans-former's mutual inductance. Two interwound coils composed of 6 metal layers are implemented to realize the transformer and fabricated using 18 µm HV CMOS process. To demonstrate the operation of the proposed transformer, the rise time (t rise ), fall time (t fall ), and propagation delay (t pro_delay ) of six chips are measured at an operating frequency of 10 MHz with a worst power consumption of 52 mW. The digital transformer is also tested at various duty cycles to ensure its suitability for power conversion applications.
ISSN:2158-1525
DOI:10.1109/ISCAS58744.2024.10558498