A Compact 24.5-32.6 GHz CMOS Frequency Doubler Based on Coupled Inductor

This brief presents analysis and design of a push-push frequency doubler utilizing coupled inductor. In order to address the challenging issues of power bandwidth and footprint of the K/Ka-band CMOS push-push doublers, the coupled inductor is proposed as series device at the gate. Compared with conv...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2024-05, Vol.71 (5), p.2609-2613
Main Authors: Ding, Yifan, Shen, Yizhu, Lin, Zhen, Hu, Sanming
Format: Article
Language:English
Subjects:
Baluns
Bandwidth
Bandwidths
CMOS
coupled inductor
Couplings
Extremely high frequencies
frequency doubler
Frequency doublers
frequency multiplier
Impedance
Inductance
Inductors
Logic gates
Power generation
push-push
Resonant frequencies
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Summary:This brief presents analysis and design of a push-push frequency doubler utilizing coupled inductor. In order to address the challenging issues of power bandwidth and footprint of the K/Ka-band CMOS push-push doublers, the coupled inductor is proposed as series device at the gate. Compared with conventional input matching techniques, both differential-mode (DM) and common-mode (CM) characteristics are utilized, where the CM characteristic of the coupled inductor is proposed to achieve wide bandwidth and high power, while provides equivalent DM inductance at fundamental frequency. For low-cost validation, the proposed doubler is fabricated in a 180-nm CMOS process. It features a compact area of 0.34\, {\mathrm{ mm}}^{2} ( 0.0031\lambda ^{2} ) in total and core area of 0.15\, {\mathrm{ mm}}^{2} ( 0.0014\lambda ^{2} ), and a measured 3-dB bandwidth of 24.5-32.6 GHz (28.4%) with an output power of 3.5-6.5 dBm. Measurement results also show that, the frequency doubler achieves a saturation output power of 7.9 dBm, and a fundamental rejection ratio higher than 34 dBc.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2024.3350774