A portable and fault-tolerant microprocessor based on the SPARC v8 architecture

The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32 bit processor based on the SPARC V8 instruction set. The processors tolerates transient SEU errors by using techniques such as TMR registers, on-chip EDAC, parity, pipeline restart, and forced c...

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Bibliographic Details
Main Author: Gaisler, J.
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
CMOS process
Cyclotrons
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Fault tolerance
Hardware
Integrated circuits
Manufacturing processes
Microprocessors
Pipelines
Prototypes
Registers
Reliability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Software prototyping
Software testing
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Description
Summary:The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32 bit processor based on the SPARC V8 instruction set. The processors tolerates transient SEU errors by using techniques such as TMR registers, on-chip EDAC, parity, pipeline restart, and forced cache miss. The first prototypes were manufactured on the Atmel ATC35 0.35 /spl mu/m CMOS process, and subjected to heavy-ion fault-injection at the Louvain Cyclotron. The heavy-ion tests showed that all of the injected errors (>100,000) were successfully corrected without timing or software impact. The device SEU threshold was measured to be below 6 MeV while ion energy-levels of up to 110 MeV were used for error injection.
DOI:10.1109/DSN.2002.1028926