A 2 A Maximum Load Current Capable 0-to-1 μF Off-chip Capacitor N-type LDO using Dual Dynamic Negative Feedback Loop and an Improved Error Amplifier

This paper proposes a low-dropout regulator (LDO) which is stable over an output capacitor (Co) range from 0 to 1 \muF. The proposed LDO uses an n-type power transistor (\mathrm{M}_{\mathrm{P}}) with a high-gain single-stage error amplifier. Since, the proposed LDO is designed as a one-pole system a...

Full description

Saved in:
Bibliographic Details
Main Authors: Ahn, Ho-Chan, Cho, Joo-Mi, Choi, Hyeon-Ji, Lee, Chan-Ho, Lee, Chan-Kyu, Hong, Sung-Wan
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Negative feedback loops
NMOS low dropout regulator
Power transistors
Regulators
Simulation
Single-pole system
Stability analysis
Transient response
Wide range of Co
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper proposes a low-dropout regulator (LDO) which is stable over an output capacitor (Co) range from 0 to 1 \muF. The proposed LDO uses an n-type power transistor (\mathrm{M}_{\mathrm{P}}) with a high-gain single-stage error amplifier. Since, the proposed LDO is designed as a one-pole system and the pole is generated by a large parasitic capacitance of MP and the output impedance of the error amplifier, this LDO can easily be compensated without using any compensation capacitor, which degrades the slew rate (SR). To improve the transient response and maintain stability over a wide range of Co, a dynamic negative feedback loop (DNFL) is used. In addition, the error amplifier adaptively boosts its transconductance (\mathrm{G}_{\mathrm{m}}) only in transition to shorten the settling time. The chip was fabricated in a 0.5-\mum CMOS process with a maximum load current of 2 A.
ISSN:2643-1319
DOI:10.1109/ESSCIRC59616.2023.10268786