Outlier Detection for Analog Tests Using Deep Learning Techniques

With the increasing demand for high reliability of products, how to prevent potential defective devices from shipping to customers is a serious issue about which more and more companies are concerned. Toward this end, many test methods have been developed to screen out outliers. However, basic stati...

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Bibliographic Details
Main Authors: Lin, Chin-Kuan, Lu, Cheng-Che, Chang, Shuo-Wen, Chu, Ying-Hua, Wu, Kai-Chiang, Chao, Mango Chia-Tso
Format: Conference Proceeding
Language:English
Subjects:
Data visualization
Deep learning
Detectors
Information filters
Measurement
Transistors
Very large scale integration
Online Access:Request full text
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Summary:With the increasing demand for high reliability of products, how to prevent potential defective devices from shipping to customers is a serious issue about which more and more companies are concerned. Toward this end, many test methods have been developed to screen out outliers. However, basic statistical paradigm may not be enough to handle the shrinking transistor size and increasingly complex circuit design. In this paper, we propose to use the concept of Z-score derived from our proposed neural network, called single density network (SDN), to define level of abnormality. We also define new metrics called self-excluded fail rate (SE fail rate) and normalized area under curve (AUC) to be our criteria to quantify and further visualize the outcome. To filter out spatially-correlated outliers, we make use of specific information of neighboring dice and encode them into our input features for the proposed SDN. A series of experimental results on industrial data reveal the effectiveness of our methodology and the better ability to identify defective outliers than existing conventional statistical approaches for a variety of analog tests.
ISSN:2375-1053
DOI:10.1109/VTS56346.2023.10139998