Loading…

Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures

Chiplet-based 2.5D systems that integrate multiple smaller chips on a single die are gaining popularity for executing both compute-and data-intensive applications. While smaller chips (chiplets) reduce fabrication costs, they also provide less functionality. Hence, manufacturing several smaller chip...

Full description

Saved in:

Bibliographic Details
Main Authors:	Sharma, Harsh, Mandal, Sumit K., Doppa, Janardhan Rao, Ogras, Umit, Pande, Partha Pratim
Format:	Conference Proceeding
Language:	English
Subjects:	2.5D Chiplet Computer architecture Costs Energy efficiency Fabrication NoP Performance evaluation PIM Topology
Online Access:	Request full text
Tags:	Add Tag No Tags, Be the first to tag this record!

cited_by
cites
container_end_page	6
container_issue
container_start_page	1
container_title
container_volume
creator	Sharma, Harsh Mandal, Sumit K. Doppa, Janardhan Rao Ogras, Umit Pande, Partha Pratim
description	Chiplet-based 2.5D systems that integrate multiple smaller chips on a single die are gaining popularity for executing both compute-and data-intensive applications. While smaller chips (chiplets) reduce fabrication costs, they also provide less functionality. Hence, manufacturing several smaller chiplets and combining them into a single system enables the functionality of a larger monolithic chip without prohibitive fabrication costs. The chiplets are connected through the network-on-interposer (NoP). Designing a high-performance and energy-efficient NoP architecture is essential as it enables large-scale chiplet integration. This paper highlights the challenges and existing solutions for designing suitable NoP architectures targeted for 2.5D systems catered to datacenter-scale applications. We also highlight the future research challenges stemming from the current state-of-the-art to make the NoP-based 2.5D systems widely applicable.
doi_str_mv	10.23919/DATE56975.2023.10137125
format	conference_proceeding
fullrecord	<record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_10137125</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10137125</ieee_id><sourcerecordid>10137125</sourcerecordid><originalsourceid>FETCH-LOGICAL-i204t-1a48b1651c06491c9a48fe3bd7810d867c983a51392e39fc8f11d07fa960d0423</originalsourceid><addsrcrecordid>eNo1j9FKwzAYRoMgOKdv4EVeIDV_0rTJZemmDiYKzuuRpn_WSteOJBP29hbUq49zLg58hFDgmZAGzOOq2q1VYUqVCS5kBhxkCUJdkQUopRnM4obcxvjFOVdSmAX5qFzX43c_HujKJutwTBhYdHZA-o7BT-FoR4c0dWE6Hzpad_1pwMQaG7Glr3a8uCkgrcKcSejSOWC8I9feDhHv_3ZJPp_Wu_qFbd-eN3W1Zb3geWJgc91AocDxIjfgzMweZdOWGniri9IZLa0CaQRK4532AC0vvTUFb3ku5JI8_HZ7RNyfQn-04bL_Py1_AHHBTwo</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures</title><source>IEEE Xplore All Conference Series</source><creator>Sharma, Harsh ; Mandal, Sumit K. ; Doppa, Janardhan Rao ; Ogras, Umit ; Pande, Partha Pratim</creator><creatorcontrib>Sharma, Harsh ; Mandal, Sumit K. ; Doppa, Janardhan Rao ; Ogras, Umit ; Pande, Partha Pratim</creatorcontrib><description>Chiplet-based 2.5D systems that integrate multiple smaller chips on a single die are gaining popularity for executing both compute-and data-intensive applications. While smaller chips (chiplets) reduce fabrication costs, they also provide less functionality. Hence, manufacturing several smaller chiplets and combining them into a single system enables the functionality of a larger monolithic chip without prohibitive fabrication costs. The chiplets are connected through the network-on-interposer (NoP). Designing a high-performance and energy-efficient NoP architecture is essential as it enables large-scale chiplet integration. This paper highlights the challenges and existing solutions for designing suitable NoP architectures targeted for 2.5D systems catered to datacenter-scale applications. We also highlight the future research challenges stemming from the current state-of-the-art to make the NoP-based 2.5D systems widely applicable.</description><identifier>EISSN: 1558-1101</identifier><identifier>DOI: 10.23919/DATE56975.2023.10137125</identifier><language>eng</language><publisher>EDAA</publisher><subject>2.5D ; Chiplet ; Computer architecture ; Costs ; Energy efficiency ; Fabrication ; NoP ; Performance evaluation ; PIM ; Topology</subject><ispartof>2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, p.1-6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10137125$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>310,311,786,790,795,796,23958,23959,25170,27958,54906,55283</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10137125$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sharma, Harsh</creatorcontrib><creatorcontrib>Mandal, Sumit K.</creatorcontrib><creatorcontrib>Doppa, Janardhan Rao</creatorcontrib><creatorcontrib>Ogras, Umit</creatorcontrib><creatorcontrib>Pande, Partha Pratim</creatorcontrib><title>Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures</title><title>2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)</title><addtitle>DATE56975</addtitle><description>Chiplet-based 2.5D systems that integrate multiple smaller chips on a single die are gaining popularity for executing both compute-and data-intensive applications. While smaller chips (chiplets) reduce fabrication costs, they also provide less functionality. Hence, manufacturing several smaller chiplets and combining them into a single system enables the functionality of a larger monolithic chip without prohibitive fabrication costs. The chiplets are connected through the network-on-interposer (NoP). Designing a high-performance and energy-efficient NoP architecture is essential as it enables large-scale chiplet integration. This paper highlights the challenges and existing solutions for designing suitable NoP architectures targeted for 2.5D systems catered to datacenter-scale applications. We also highlight the future research challenges stemming from the current state-of-the-art to make the NoP-based 2.5D systems widely applicable.</description><subject>2.5D</subject><subject>Chiplet</subject><subject>Computer architecture</subject><subject>Costs</subject><subject>Energy efficiency</subject><subject>Fabrication</subject><subject>NoP</subject><subject>Performance evaluation</subject><subject>PIM</subject><subject>Topology</subject><issn>1558-1101</issn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2023</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1j9FKwzAYRoMgOKdv4EVeIDV_0rTJZemmDiYKzuuRpn_WSteOJBP29hbUq49zLg58hFDgmZAGzOOq2q1VYUqVCS5kBhxkCUJdkQUopRnM4obcxvjFOVdSmAX5qFzX43c_HujKJutwTBhYdHZA-o7BT-FoR4c0dWE6Hzpad_1pwMQaG7Glr3a8uCkgrcKcSejSOWC8I9feDhHv_3ZJPp_Wu_qFbd-eN3W1Zb3geWJgc91AocDxIjfgzMweZdOWGniri9IZLa0CaQRK4532AC0vvTUFb3ku5JI8_HZ7RNyfQn-04bL_Py1_AHHBTwo</recordid><startdate>202304</startdate><enddate>202304</enddate><creator>Sharma, Harsh</creator><creator>Mandal, Sumit K.</creator><creator>Doppa, Janardhan Rao</creator><creator>Ogras, Umit</creator><creator>Pande, Partha Pratim</creator><general>EDAA</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>202304</creationdate><title>Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures</title><author>Sharma, Harsh ; Mandal, Sumit K. ; Doppa, Janardhan Rao ; Ogras, Umit ; Pande, Partha Pratim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i204t-1a48b1651c06491c9a48fe3bd7810d867c983a51392e39fc8f11d07fa960d0423</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2023</creationdate><topic>2.5D</topic><topic>Chiplet</topic><topic>Computer architecture</topic><topic>Costs</topic><topic>Energy efficiency</topic><topic>Fabrication</topic><topic>NoP</topic><topic>Performance evaluation</topic><topic>PIM</topic><topic>Topology</topic><toplevel>online_resources</toplevel><creatorcontrib>Sharma, Harsh</creatorcontrib><creatorcontrib>Mandal, Sumit K.</creatorcontrib><creatorcontrib>Doppa, Janardhan Rao</creatorcontrib><creatorcontrib>Ogras, Umit</creatorcontrib><creatorcontrib>Pande, Partha Pratim</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sharma, Harsh</au><au>Mandal, Sumit K.</au><au>Doppa, Janardhan Rao</au><au>Ogras, Umit</au><au>Pande, Partha Pratim</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures</atitle><btitle>2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)</btitle><stitle>DATE56975</stitle><date>2023-04</date><risdate>2023</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><eissn>1558-1101</eissn><abstract>Chiplet-based 2.5D systems that integrate multiple smaller chips on a single die are gaining popularity for executing both compute-and data-intensive applications. While smaller chips (chiplets) reduce fabrication costs, they also provide less functionality. Hence, manufacturing several smaller chiplets and combining them into a single system enables the functionality of a larger monolithic chip without prohibitive fabrication costs. The chiplets are connected through the network-on-interposer (NoP). Designing a high-performance and energy-efficient NoP architecture is essential as it enables large-scale chiplet integration. This paper highlights the challenges and existing solutions for designing suitable NoP architectures targeted for 2.5D systems catered to datacenter-scale applications. We also highlight the future research challenges stemming from the current state-of-the-art to make the NoP-based 2.5D systems widely applicable.</abstract><pub>EDAA</pub><doi>10.23919/DATE56975.2023.10137125</doi><tpages>6</tpages></addata></record>
fulltext	fulltext_linktorsrc
identifier	EISSN: 1558-1101
ispartof	2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, p.1-6
issn	1558-1101
language	eng
recordid	cdi_ieee_primary_10137125
source	IEEE Xplore All Conference Series
subjects	2.5D Chiplet Computer architecture Costs Energy efficiency Fabrication NoP Performance evaluation PIM Topology
title	Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures
url	http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-09-22T17%3A36%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Achieving%20Datacenter-scale%20Performance%20through%20Chiplet-based%20Manycore%20Architectures&rft.btitle=2023%20Design,%20Automation%20&%20Test%20in%20Europe%20Conference%20&%20Exhibition%20(DATE)&rft.au=Sharma,%20Harsh&rft.date=2023-04&rft.spage=1&rft.epage=6&rft.pages=1-6&rft.eissn=1558-1101&rft_id=info:doi/10.23919/DATE56975.2023.10137125&rft_dat=%3Cieee_CHZPO%3E10137125%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i204t-1a48b1651c06491c9a48fe3bd7810d867c983a51392e39fc8f11d07fa960d0423%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=10137125&rfr_iscdi=true