Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures

Chiplet-based 2.5D systems that integrate multiple smaller chips on a single die are gaining popularity for executing both compute-and data-intensive applications. While smaller chips (chiplets) reduce fabrication costs, they also provide less functionality. Hence, manufacturing several smaller chip...

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Bibliographic Details
Main Authors: Sharma, Harsh, Mandal, Sumit K., Doppa, Janardhan Rao, Ogras, Umit, Pande, Partha Pratim
Format: Conference Proceeding
Language:English
Subjects:
2.5D
Chiplet
Computer architecture
Costs
Energy efficiency
Fabrication
NoP
Performance evaluation
PIM
Topology
Online Access:Request full text
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Summary:Chiplet-based 2.5D systems that integrate multiple smaller chips on a single die are gaining popularity for executing both compute-and data-intensive applications. While smaller chips (chiplets) reduce fabrication costs, they also provide less functionality. Hence, manufacturing several smaller chiplets and combining them into a single system enables the functionality of a larger monolithic chip without prohibitive fabrication costs. The chiplets are connected through the network-on-interposer (NoP). Designing a high-performance and energy-efficient NoP architecture is essential as it enables large-scale chiplet integration. This paper highlights the challenges and existing solutions for designing suitable NoP architectures targeted for 2.5D systems catered to datacenter-scale applications. We also highlight the future research challenges stemming from the current state-of-the-art to make the NoP-based 2.5D systems widely applicable.
ISSN:1558-1101
DOI:10.23919/DATE56975.2023.10137125