Transferable Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs

Monolithic 3D (M3D) integration is a promising technology for achieving high performance and low power consumption. However, the limitations of current M3D fabrication flows lead to performance degradation of devices in the top tier and unreliable interconnects between tiers. Fault localization at t...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2023-05, p.1-1
Main Authors: Hung, Shao-Chun, Banerjee, Sanmitra, Chaudhuri, Arjun, Kim, Jinwoo, Lim, Sung Kyu, Chakrabarty, Krishnendu
Format: Article
Language:English
Subjects:
Benchmark testing
Circuit faults
Delays
Diagnosis
Graph neural network
Graph neural networks
Integrated circuits
Location awareness
Monolithic 3D integration
Three-dimensional displays
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Summary:Monolithic 3D (M3D) integration is a promising technology for achieving high performance and low power consumption. However, the limitations of current M3D fabrication flows lead to performance degradation of devices in the top tier and unreliable interconnects between tiers. Fault localization at the tier level is therefore necessary to enhance yield learning, For example, tier-level localization can enable targeted diagnosis and process optimization efforts. In this paper, we develop a graph neural network-based diagnosis framework to efficiently localize faults to a device tier. The proposed framework can be used to provide rapid feedback to the foundry and help enhance the quality of diagnosis reports generated by commercial tools. Results for four M3D benchmarks, with and without response compaction, show that the proposed solution achieves up to 32.86% improvement in diagnostic resolution with less than 1% loss of accuracy, compared to results from commercial tools. The proposed framework has also been demonstrated to be transferable to perform diagnosis on various design configurations without performance degradation.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2023.3275532