Impact of wafer charging on hot carrier reliability and optimization of latent damage detection methodology in advanced CMOS technologies

We have studied the possibility to use hot carrier stresses to reveal the latent damage due to Wafer Charging during plasma process steps in 0.18 μm and 0.6 μm CMOS technologies. We have investigated various hot carrier conditions in N- and PMOSFETs and compared the results to classical parametric s...

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Bibliographic Details
Published in:Microelectronics and reliability 2005-03, Vol.45 (3), p.487-492
Main Authors: Goguenheim, D., Bravaix, A., Gomri, S., Moragues, J.M., Monserie, C., Legrand, N., Boivin, P.
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Engineering Sciences
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Testing, measurement, noise and reliability
Transistors
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Summary:We have studied the possibility to use hot carrier stresses to reveal the latent damage due to Wafer Charging during plasma process steps in 0.18 μm and 0.6 μm CMOS technologies. We have investigated various hot carrier conditions in N- and PMOSFETs and compared the results to classical parametric studies and short electron injections under high electric field in Fowler–Nordheim regime, using a sensitivity factor defined as the relative shift towards a reference protected device. The most accurate monitor remains the threshold voltage and the most sensitive configuration is found to be short hot electron injections in PMOSFET’s. The ability of very short hot electron injections to reveal charging damage is even more evidenced in thinner oxides and the better sensitivity of PMOSFET is explained in terms of conditions encountered by the device during the charging process step.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2004.09.004