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Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic s...
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| Published in: | IEEE transactions on very large scale integration (VLSI) systems 2006-12, Vol.14 (12), p.1309-1321 |
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| cited_by | cdi_FETCH-LOGICAL-c354t-ea9905f3806001f7a681bfcc145f190ad37a27a0af0d7285b7603e3176c1a3893 |
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| cites | cdi_FETCH-LOGICAL-c354t-ea9905f3806001f7a681bfcc145f190ad37a27a0af0d7285b7603e3176c1a3893 |
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| container_issue | 12 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Goel, S. Kumar, A. Bayoumi, M.A. |
| description | We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders |
| doi_str_mv | 10.1109/TVLSI.2006.887807 |
| format | article |
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A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2006.887807</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Adders ; Applied sciences ; Arithmetic ; Categories ; Circuit noise ; Circuit properties ; Circuits ; CMOS logic circuits ; Construction ; deep-submicrometer design ; Design ; Design engineering ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Display ; Driving ; Electric breakdown ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Energy efficiency ; Exact sciences and technology ; hybrid- CMOS design style ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Logic ; Logic design ; Low voltage ; low-power ; Microprocessors ; noise ; Robustness ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Very large scale integration</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2006-12, Vol.14 (12), p.1309-1321</ispartof><rights>2007 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c354t-ea9905f3806001f7a681bfcc145f190ad37a27a0af0d7285b7603e3176c1a3893</citedby><cites>FETCH-LOGICAL-c354t-ea9905f3806001f7a681bfcc145f190ad37a27a0af0d7285b7603e3176c1a3893</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4052347$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,786,790,27957,27958,55147</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=18458379$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Goel, S.</creatorcontrib><creatorcontrib>Kumar, A.</creatorcontrib><creatorcontrib>Bayoumi, M.A.</creatorcontrib><title>Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders</description><subject>Adders</subject><subject>Applied sciences</subject><subject>Arithmetic</subject><subject>Categories</subject><subject>Circuit noise</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>CMOS logic circuits</subject><subject>Construction</subject><subject>deep-submicrometer design</subject><subject>Design</subject><subject>Design engineering</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Display</subject><subject>Driving</subject><subject>Electric breakdown</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Energy efficiency</subject><subject>Exact sciences and technology</subject><subject>hybrid- CMOS design style</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Logic</subject><subject>Logic design</subject><subject>Low voltage</subject><subject>low-power</subject><subject>Microprocessors</subject><subject>noise</subject><subject>Robustness</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><recordid>eNpdkEFr2zAYhk1ZoV26H1B2EYPRy5x-sixLOpY0WQsphaXpVcjyp6Dg2JlkH_LvpzRhg-kiIT3fy6sny24pTCkFdf_2vlw9TwuAaiqlkCAusmvKuchVWp_SGSqWy4LCVfY5xi0ALUsF19n2EaPfdKR35Fdfj3H4QeYdhs0hnzvnrcduIIuxbclD02CIxPWBPCLu89VY77wN_Q4HPF59pKyj7zbk6VAH3-Szl9cVWfYbb8lqOLR4k10600b8ct4n2Xoxf5s95cvXn8-zh2VuGS-HHI1SwB2TUKWWTphK0tpZS0vuqALTMGEKYcA4aEQheS0qYMioqCw1TCo2ye5OufvQ_x4xDnrno8W2NR32Y9RSqpICcJbIb_-R234MXSqnFS2SIZBFgugJSp-NMaDT--B3Jhw0BX10rz_c66N7fXKfZr6fg020pnXBdNbHf4Oy5JKJY9WvJ84j4t_nEnjBSsH-AGzmi2Q</recordid><startdate>20061201</startdate><enddate>20061201</enddate><creator>Goel, S.</creator><creator>Kumar, A.</creator><creator>Bayoumi, M.A.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20061201</creationdate><title>Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style</title><author>Goel, S. ; Kumar, A. ; Bayoumi, M.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c354t-ea9905f3806001f7a681bfcc145f190ad37a27a0af0d7285b7603e3176c1a3893</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Adders</topic><topic>Applied sciences</topic><topic>Arithmetic</topic><topic>Categories</topic><topic>Circuit noise</topic><topic>Circuit properties</topic><topic>Circuits</topic><topic>CMOS logic circuits</topic><topic>Construction</topic><topic>deep-submicrometer design</topic><topic>Design</topic><topic>Design engineering</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Display</topic><topic>Driving</topic><topic>Electric breakdown</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Energy efficiency</topic><topic>Exact sciences and technology</topic><topic>hybrid- CMOS design style</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Logic</topic><topic>Logic design</topic><topic>Low voltage</topic><topic>low-power</topic><topic>Microprocessors</topic><topic>noise</topic><topic>Robustness</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Goel, S.</creatorcontrib><creatorcontrib>Kumar, A.</creatorcontrib><creatorcontrib>Bayoumi, M.A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Xplore / Electronic Library Online (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Goel, S.</au><au>Kumar, A.</au><au>Bayoumi, M.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2006-12-01</date><risdate>2006</risdate><volume>14</volume><issue>12</issue><spage>1309</spage><epage>1321</epage><pages>1309-1321</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><notes>ObjectType-Article-2</notes><notes>SourceType-Scholarly Journals-1</notes><notes>ObjectType-Feature-1</notes><notes>content type line 23</notes><abstract>We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2006.887807</doi><tpages>13</tpages></addata></record> |
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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2006-12, Vol.14 (12), p.1309-1321 |
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| source | IEEE Electronic Library (IEL) Journals |
| subjects | Adders Applied sciences Arithmetic Categories Circuit noise Circuit properties Circuits CMOS logic circuits Construction deep-submicrometer design Design Design engineering Design. Technologies. Operation analysis. Testing Digital circuits Display Driving Electric breakdown Electric, optical and optoelectronic circuits Electronic circuits Electronics Energy efficiency Exact sciences and technology hybrid- CMOS design style Integrated circuits Integrated circuits by function (including memories and processors) Logic Logic design Low voltage low-power Microprocessors noise Robustness Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Very large scale integration |
| title | Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style |
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