Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic s...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2006-12, Vol.14 (12), p.1309-1321
Main Authors: Goel, S., Kumar, A., Bayoumi, M.A.
Format: Article
Language:English
Subjects:
Adders
Applied sciences
Arithmetic
Categories
Circuit noise
Circuit properties
Circuits
CMOS logic circuits
Construction
deep-submicrometer design
Design
Design engineering
Design. Technologies. Operation analysis. Testing
Digital circuits
Display
Driving
Electric breakdown
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Energy efficiency
Exact sciences and technology
hybrid- CMOS design style
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic
Logic design
Low voltage
low-power
Microprocessors
noise
Robustness
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Very large scale integration
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Summary:We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2006.887807