Balancing of Peak Currents Between Paralleled SiC MOSFETs by Drive-Source Resistors and Coupled Power-Source Inductors

The peak currents between two paralleled SiC MOSFETs could differ significantly due to the mismatch in threshold voltages V th . The method described herein employs passive compensation (drive-source resistors and coupled power-source inductors) to balance the peak currents using one gate driver, no...

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Bibliographic Details
Published in:IEEE transactions on industrial electronics (1982) 2017-10, Vol.64 (10), p.8334-8343
Main Authors: Yincan Mao, Zichen Miao, Chi-Ming Wang, Ngo, Khai D. T.
Format: Article
Language:English
Subjects:
Circuits
Current balancing
Current sharing
Electric potential
Inductance
Inductors
Logic gates
magnetic coupling
MOSFET
MOSFETs
parallel connection
Passive components
Resistors
SiC MOSFET
Stress
Switching
Switching loss
Transient analysis
Unbalance
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Summary:The peak currents between two paralleled SiC MOSFETs could differ significantly due to the mismatch in threshold voltages V th . The method described herein employs passive compensation (drive-source resistors and coupled power-source inductors) to balance the peak currents using one gate driver, no sensors, and no feedback- without increasing total switching loss when equivalent gate-drive resistance (R g + 0.5R k ) is kept constant. This solution works for both polarities of V th mismatch and forces balancing from the first current peak. The extra voltage stress from this solution is mitigated by negative coupling. The passive components (resistance, self-inductance, and mutual inductance) are determined by an equation involving the magnitude of V th mismatch, current rise time, and unbalance percentage. The influence of other parasitic inductances on current sharing is analyzed. The robustness of this passive balancing method is experimentally verified by a prototype with a significant amount of parasitic inductances. Test results show that the difference of peak currents can be reduced from 15% to 3% without changing the switching loss and voltage stress.
ISSN:0278-0046
1557-9948
DOI:10.1109/TIE.2017.2716868